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82546EB Dual Port Gigabit Ethernet Controller
Networking Silicon
Datasheet
Revision 1.4 June 2003
Revision History
Revision 1.4 1.3 Date June 2003 Apr 2003 Description Updated Table 41 "Grounds and No Connect Signals." Added desicriptions to the Clock View and Factory Test Pin JTAG test signals that were inadvetently omitted in Revision 1.2 (Section 3.8, "JTAG Test Interface Signals" and Table 37 "JTAG Test Interface Signals"). Initial public release.
1.2
Apr 2003
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82546EB may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) 2003, Intel Corporation. *Third-party brands and names are the property of their respective owners.
Datasheet
Networking Silicon -- 82546EB
Contents
1.0 Introduction......................................................................................................................... 1 1.1 1.2 1.3 2.0 Document Scope ...................................................................................................2 Reference Documents........................................................................................... 2 Product Code ........................................................................................................ 3
Features of the 82546EB Dual Port Gigabit Ethernet Controller........................................ 4 2.1 2.2 2.3 2.4 2.5 2.6 2.7 PCI Features ......................................................................................................... 4 MAC Specific Features.......................................................................................... 4 PHY Specific Features .......................................................................................... 5 Host Offloading Features ...................................................................................... 5 Manageability Features ......................................................................................... 6 Additional Device Features ................................................................................... 6 Technology Features............................................................................................. 7
3.0
Signal Descriptions............................................................................................................. 8 3.1 3.2 Signal Type Definitions.......................................................................................... 8 PCI Bus Interface .................................................................................................. 8 3.2.1 PCI Address, Data and Control Signals ................................................... 8 3.2.2 Arbitration Signals .................................................................................. 10 3.2.3 Interrupt Signals .....................................................................................10 3.2.4 System Signals....................................................................................... 10 3.2.5 Error Reporting Signals .......................................................................... 11 3.2.6 Power Management Signals ..................................................................11 3.2.7 Impedance Compensation Signals......................................................... 11 3.2.8 SMB Signals........................................................................................... 11 EEPROM Interface Signals ................................................................................. 12 Flash Interface Signals........................................................................................ 12 Miscellaneous Signals......................................................................................... 12 3.5.1 LED Signals............................................................................................12 3.5.2 Software Definable Signals .................................................................... 13 PHY Signals ........................................................................................................13 3.6.1 Crystal Signals ....................................................................................... 13 3.6.2 PHY Analog Signals ............................................................................... 14 Serializer / Deserializer Signals........................................................................... 15 JTAG Test Interface Signals ............................................................................... 15 Power Supply Connections ................................................................................. 16 3.9.1 Power Support Signals........................................................................... 16 3.9.2 Digital Supplies....................................................................................... 16 3.9.3 Analog Supplies .....................................................................................16 3.9.4 Ground and No Connects.......................................................................17
3.3 3.4 3.5
3.6
3.7 3.8 3.9
4.0
Voltage, Temperature, and Timing Specifications............................................................ 18 4.1 4.2 4.3 4.4 4.5 Targeted Absolute Maximum Ratings ................................................................. 18 Recommended Operating Conditions ................................................................. 18 DC Specifications ................................................................................................ 19 AC Characteristics............................................................................................... 21 Serial Interface Specifications ............................................................................. 22
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82546EB -- Networking Silicon
4.6
Timing Specifications .......................................................................................... 23 4.6.1 PCI/PCI-X Bus Interface ........................................................................ 23 4.6.2 Link Interface Timing .............................................................................. 26 4.6.3 Flash Interface ....................................................................................... 29 4.6.4 EEPROM Interface................................................................................. 30
5.0
Package and Pinout Information ...................................................................................... 31 5.1 5.2 5.3 5.4 5.5 Device Identification ........................................................................................... 31 Package Information ........................................................................................... 32 Thermal Specifications ........................................................................................ 33 Ball Mapping Diagram ......................................................................................... 34 Pinout Information ............................................................................................... 35
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Datasheet
Networking Silicon -- 82546EB
Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Absolute Maximum Ratings................................................................................. 18 Recommended Operating Conditions ................................................................. 18 DC Characteristics .............................................................................................. 19 Power Supply Characteristics ............................................................................. 19 AC Characteristics: 3.3 V Interfacing ..................................................................21 25 MHz Clock Input Requirements...................................................................... 21 Link Interface Clock Requirements ..................................................................... 21 EEPROM Interface Clock Requirements ............................................................ 21 AC Test Loads for General Output Pins.............................................................. 21 Driver Characteristics ..........................................................................................22 Receiver Characteristics .....................................................................................22 PCI/PCI-X Bus Interface Clock Parameters ........................................................ 23 PCI/PCI-X Bus Interface Timing Parameters ...................................................... 23 PCI Bus Interface Timing Measurement Conditions ........................................... 24 Rise and Fall Times............................................................................................. 26 Transmit Interface Timing.................................................................................... 27 Receive Interface Timing.....................................................................................28 Flash Read Operation Timing ............................................................................. 29 Flash Write Operation Timing..............................................................................30 Link Interface Clock Requirements ..................................................................... 30 Link Interface Clock Requirements ..................................................................... 30 Thermal Characteristics ...................................................................................... 33 PCI Address, Data, and Control Signals ............................................................. 35 PCI Arbitration Signals ........................................................................................ 35 Interrupt Signals .................................................................................................. 36 System Signals.................................................................................................... 36 Error Reporting Signals ....................................................................................... 36 Power Management Signals ............................................................................... 36 Impedance Compensation Signals...................................................................... 36 SMB Signals........................................................................................................36 EEPROM Interface Signals ................................................................................. 36 Flash Interface Signals........................................................................................ 37 LED Signals......................................................................................................... 37 Software Definable Signals ................................................................................. 37 Crystal Signals .................................................................................................... 37 PHY Signals ........................................................................................................37 Serializer / Deserializer Signals........................................................................... 38 JTAG Test Interface Signals ............................................................................... 38 Power Support Signals........................................................................................ 38 Digital Power Signals ..........................................................................................39 Analog Power Signals ......................................................................................... 39 Grounds and No Connect Signals .......................................................................40 Reserved Signals ................................................................................................ 41
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82546EB -- Networking Silicon
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Networking Silicon -- 82546EB
1.0
Introduction
The Intel(R) 82546EB Dual Port Gigabit Ethernet Controller is a single, compact component with two full integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. The Intel(R) 82546EB enables dual port Gigabit Ethernet implementations in a very small area and can be used for desktop and workstation PC network designs with critical space constraints. The Intel(R) 82546EB integrates Intel's fourth generation gigabit MAC and PHY to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving two channels of data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition, it provides a 64-bit wide direct Peripheral Component Interconnect (PCI) 2.2 and PCI-X 1.0a compliant interface capable of operating at frequencies up to 133 MHz. The 82546EB also delivers a dual port PCI-X solution without added bridge latency. The Intel(R) 82546EB on-board System Management Bus (SMB) port enables network manageability implementations required by information technology personnel for remote control and alerting through the LAN. Using the SMB, management packets can be routed to or from a management processor. The SMB port enables industry standards, such as Intelligent Platform Management Interface (IPMI) and Alert Standard Format (ASF), to be implemented using the 82546EB. In addition, on chip ASF 1.0 circuitry provides alerting and remote control capabilities with standardized interfaces. The 82546EB Dual Port Gigabit Ethernet Controller architecture is designed to deliver high performance and PCI/PCI-X bus efficiency. Wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. Combining a parallel and pipelined logic architecture optimized for Gigabit Ethernet and independent transmit and receive queues, the 82546EB controller efficiently handles packets with minimum latency. The 82546EB controller includes advanced interrupt handling features to limit PCI bus traffic and a PCI interface that maximizes the use of bursts for efficient bus usage. The 82546EB is able to cache up to 64 packet descriptors in a single burst for efficient PCI bandwidth use. A large 64 Kbyte on-chip packet buffer maintains superior performance as available PCI bandwidth changes. By using hardware acceleration, the controller is able to offload tasks, such as checksum calculations and TCP segmentation, from the host processor.
Datasheet
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82546EB -- Networking Silicon
The 82546EBis packaged in a 21 mm x 21 mm 364-ball grid array and footprint compatible with the Intel(R) 82544GC Gigabit Ethernet Controller. Figure 1. Gigabit Ethernet Controller Block Diagram
MDI Interface A MDI Interface B
1000Base-T PHY Interfaces
Design For Test Interface External TBI Interface
10/100/1000 PHY
GMII/ MDIO MII
10/100/1000 PHY
GMII/ MDIO MII
SM Bus Interface EEPROM Interface Flash Interface LED's S/W Defined Pins
LED's S/W Defined Pins
Device Funct. #0 MAC/Controller (LAN A)
Device Funct. #1 MAC/Controller (LAN B)
PCI (64 bit,33/66MHz); PCI-X (133MHz)
1.1
Document Scope
This document contains datasheet specifications for the 82546EB Dual Port Gigabit Ethernet Controller, which includes signal descriptions, DC and AC parameters, packaging data, and pinout information.
1.2
Reference Documents
It is assumed that the designer is acquainted with high-speed design and board layout techniques. Document that may provide additional information are:
* * * * * * *
PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group. PCI-X Specification, Revision 1.0a, PCI Special Interest Group. PCI Bus Power Management Interface Specification, Rev. 1.1, PCI Special Interest Group. IEEE Standard 802.3, 1996 Edition, Institute of Electrical and Electronics Engineers (IEEE). IEEE Standard 802.3u, 1995 Edition, Institute of Electrical and Electronics Engineers (IEEE). IEEE Standard 802.3x, 1997 Edition, Institute of Electrical and Electronics Engineers (IEEE). IEEE Standard 802.3z, 1998 Edition, Institute of Electrical and Electronics Engineers (IEEE).
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Datasheet
Networking Silicon -- 82546EB
* IEEE Standard 802.3ab, 1999 Edition, Institute of Electrical and Electronics Engineers
(IEEE).
1.3
Product Code
The product ordering code for the 82546EB is: FW82546EB.
Datasheet
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82546EB -- Networking Silicon
2.0
Features of the 82546EB Dual Port Gigabit Ethernet Controller
PCI Features
Features PCI-X Revision 1.0a support for frequencies up to 133 MHz Multi-function PCI device * * * * PCI Revision 2.2 support for 32-bit wide or 64-bit wide interface at 33 MHz and 66 MHz Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands as well as PCI-X MRD, MRB, and MWB commands * Benefits Bandwidth support for more headroom allowance for Gigabit Ethernet One electrical load on the bus PCI/PCI-X bridge component not required for a dual port design implementation Application flexibility for LAN on Motherboard (LOM) or embedded solutions 64-bit addressing for systems with more than 4 Gbytes of physical memory Efficient bus operations
2.1
*
2.2
MAC Specific Features
Features Low-latency transmit and receive queues IEEE 802.3x compliant flow control support with software controllable pause times and threshold values Caches up to 64 packet descriptors in a single burst Programable host memory receive buffers (256 Bytes to 16 Kbytes) and cache line size (16 Bytes to 256 Bytes) Wide, optimized internal data path architecture (128 bits) Dual 64 Kbytes configurable Transmit and Receive FIFO buffers Descriptor ring management hardware for transmit and receive Optimized descriptor fetching and write-back mechanisms Mechanism available for reducing interrupts generated by transmit and receive operations Support for transmission and reception of packets up to 16 Kbytes * * * * * * * * * * * Benefits Network packets handled without waiting or buffer overflow. Control over the transmissions of pause frames through software or hardware triggering Frame loss reduced from receive overruns Efficient use of PCI bandwidth Efficient use of PCI bandwidth Low latency data handling Superior DMA transfer rate performance No external FIFO memory requirements FIFO size adjustable to application Simple software programming model Efficient system memory and use of PCI bandwidth Maximizes system performance and throughput Enables jumbo frames
* *
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Networking Silicon -- 82546EB
2.3
PHY Specific Features
Features Integrated PHY for 10/100/1000 Mbps full and half duplex operation IEEE 802.3ab Auto-Negotiation support IEEE 802.3ab PHY compliance and compatibility State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and crosstalk cancellation PHY ability to automatically detect polarity and cable lengths and MDI versus MDI-X cable at all speeds * * * * * * * Benefits Smaller footprint and lower power dissipation compared to multi-chip MAC and PHY solutions Automatic link configuration including speed, duplex, and flow control Robust operation over the installed base of Category-5 (CAT-5) twisted pair cabling Robust performance in noisy environments Tolerance of common electrical signal impairments Easier network installation and maintenance End-to-end wiring tolerance
2.4
Host Offloading Features
Features Transmit and receive IP, TCP and UDP checksum offloading capabilities Transmit TCP segmentation * * * * * Advanced packet filtering * * IEEE 802.1q VLAN support with VLAN tag insertion, stripping and packet filtering for up to 4096 VLAN tags Descriptor ring management hardware for transmit and receive 16-Kbyte jumbo frame support Interrupt coalescing (multiple packets per interrupt) * * Benefits Lower CPU utilization Increased throughput and lower CPU utilization Large send offload feature (in Microsoft* Windows* XP) compatible 16 exact matched packets (unicast or multicast) 4096-bit hash filter for multicast frames Promiscuous (unicast and multicast) transfer mode support Optical filtering of invalid frames Ability to create multiple virtual LAN segments Optimized fetching and write-back mechanisms for efficient system memory and PCI bandwidth usage High throughput for large data transfers on networks supporting jumbo frames Increased throughput by reducing interrupts generated by transmit and receive operations
* *
Datasheet
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82546EB -- Networking Silicon
2.5
Manageability Features
Features Manageability features on both ports: SMB port, ASF 1.0, ACPI, Wake on LAN, and PXE On-board SMB port Preboot eXecution Environment (PXE) Flash interface support (32-bit nd 64-bit) Compliance with PCI Power Management 1.1 and ACPI 2.0 register set compliant including: * * * D0 and D3 power states Network Device Class Power Management Specification 1.1 PCI Specification 2.2 * * * Easy system monitoring with industry standard consoles Remote network management capabilities through DMI 2.0 and SNMP software Packet recognition and wake-up for NIC and LOM applications without software configuration * PCI power management capability requirements for PC and embedded applications * * * Benefits Network management flexibility Enables IPMI and ASF implementations Allows packets routing to and from either LAN port and a server management processor Local Flash interface for PXE image
*
SNMP and RMON statistic counters SDG 3.0, WfM 2.0, and PC2001 compliance Wake on LAN support
2.6
Additional Device Features
Features * * Two complete gigabit Ethernet connections in a single device * * * Eight activity and link indication outputs that directly drive LEDs Internal PLL for clock generation (use either a 25 MHz crystal or a 25 MHz oscillator) JTAG (IEEE 1149.1) Test Access Port built in silicon On-chip power control circuitry * Eight software definable pins * * Benefits High availability using one port for failover Higher throughput than single gigabit Ethernet port Lower latency due to one electrical load on the bus Saves critical board space Reduced multi-port gigabit Ethernet costs Link and activity indications (10, 100, and 1000 Mbps) on each port Lower component count and system cost Simplified testing using boundary scan Reduced number of on-board power supply regulators Simplified power supply design Additional flexibility for LEDs or other low speed I/O devices
* * *
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Networking Silicon -- 82546EB
Features Supports little endian byte ordering for both 32 and 64 bit systems and big endian byte ordering for 64 bit systems Provides loopback capabilities Single-pin LAN disable function * * *
Benefits Portable across application architectures Validates silicon integrity Allows LAN port enabling and disabling through BIOS control (OS not required) for both ports
2.7
Technology Features
Features 364-pin Ball Grid Array (BGA) package Footprint compatible with the 82544GC, 82545EM, and 82545GM single port gigabit Ethernet controllers Implemented in 0.15u CMOS process 0 C to 55 C (maximum) operating temperature Heat sink or forced airflow not required 65 C to 140 C storage temperature range 3.3 V PCI signaling with an average power dissipation of 3.5 W * Lower power requirements * Simple thermal design * * * Benefits 21 mm x 21 mm component makes LOM designs easier Single port or dual port implementation on the same board with minor option changes. Offers lowest geometry to minimize power and size while maintaining Intel quality reliability standards
Datasheet
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82546EB -- Networking Silicon
3.0
Note:
Signal Descriptions
The targeted signal names are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design.
3.1
Signal Type Definitions
The signals of the 82546EB controller are electrically defined as follows:
Name I O TS Input. Standard input only digital signal. Output. Standard output only digital signal. Tri-state. Bi-directional three-state digital input/output signal. Sustained Tri-state. Sustained digital three-state signal driven by one agent at a time. STS An agent driving the STS pin low must actively drive it high for at least one clock before letting it float. The next agent of the signal cannot drive the pin earlier than one clock after it has been released by the previous agent. Open Drain. Wired-OR with other agents. OD The signaling agent asserts the OD signal, but the signal is returned to the inactive state by a weak pull-up resistor. The pull-up resistor may require two or three clock periods to fully restore the signal to the de-asserted state. Analog. PHY analog data signal. Power. Power connection, voltage reference, or other reference connection. Reserved. Definition
A P R
3.2
PCI Bus Interface
When the Reset signal (RST#) is asserted, the 82546EB will not drive any PCI output or bidirectional pins except the Power Management Event signal (PME#).
3.2.1
PCI Address, Data and Control Signals
Symbol
Type
Name and Function Address and Data. Address and data signals are multiplexed on the same PCI pins. A bus transaction includes an address phase followed by one or more data phases. The address phase is the clock cycle when the Frame signal (FRAME#) is asserted low. During the address phase AD[63:0] contain a physical address (64 bits). For I/O, this is a byte address, and for configuration and memory, a DWORD address. The 82546EB device uses little endian byte ordering. During data phases, AD[7:0] contain the least significant byte (LSB) and AD[63:56] contain the most significant byte (MSB). The 82546EBcontroller may optionally be connected to a 32-bit PCI bus. On the 32-bit bus, AD[63:32] and other signals corresponding to the high order byte lanes do not participate in the bus cycle.
AD[63:0]
TS
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Datasheet
Networking Silicon -- 82546EB
Symbol
Type
Name and Function Bus Command and Byte Enables. Bus command and byte enable signals are multiplexed on the same PCI pins. During the address phase of a transaction, CBE[7:0]# define the bus command. In the data phase, CBE[7:0]# are used as byte enables. The byte enables are valid for the entire data phase and determine which byte lanes contain meaningful data. CBE0# applies to byte 0 (LSB) and CBE7# applies to byte 7 (MSB). Parity. The Parity signal is issued to implement even parity across AD[31:0] and CBE[3:0]#. PAR is stable and valid one clock after the address phase. During data phases, PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted after a read transaction. Once PAR is valid, it remains valid until one clock after the completion of the current data phase. When the 82546EB controller is a bus master, it drives PAR for address and write data phases, and as a slave device, drives PAR for read data phases. Parity 64. The Parity 64 signal is issued to implement even parity across AD[63:32] and CBE[7:4]#. PAR64 is stable and valid one clock after the address phase. During data phases, PAR64 is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted after a read transaction. Once PAR64 is valid, it remains valid until one clock after the completion of the current data phase. When the 82546EB controller is a bus master, it drives PAR64 for address and write data phases, and as a slave device, drives PAR64 for read data phases. Cycle Frame. 82546EB device to indicate the beginning and length of an access and indicate the beginning of a bus transaction. While FRAME# is asserted, data transfers continue. FRAME# is de-asserted when the transaction is in the final data phase. Initiator Ready. Initiator Ready indicates the ability of the 82546EB controller (as bus master device) to complete the current data phase of the transaction. IRDY# is used in conjunction with the Target Ready signal (TRDY#). The data phase is completed on any clock when both IRDY# and TRDY# are asserted. During the write cycle, IRDY# indicates that valid data is present on AD[63:0]. For a read cycle, it indicates the master is ready to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. The 82546EB controller drives IRDY# when acting as a master and samples it when acting as a slave. Target Ready. The Target Ready signal indicates the ability of the 82546EB controller (as a selected device) to complete the current data phase of the transaction. TRDY# is used in conjunction with the Initiator Ready signal (IRDY#). A data phase is completed on any clock when both TRDY# and IRDY# are sampled asserted. During a read cycle, TRDY# indicates that valid data is present on AD[63:0]. For a write cycle, it indicates the target is ready to accept data. Wait cycles are inserted until both IRDY# and TRDY# are asserted together. The 82546EB device drives TRDY# when acting as a slave and samples it when acting as a master. Stop. The Stop signal indicates the current target is requesting the master to stop the current transaction. As a slave, the 82546EB controller drives STOP# to request the bus master to stop the transaction. As a master, the 82546EB controller receives STOP# from the slave to stop the current transaction. Initialization Device Select. The Initialization Device Select signal is used by the 82546EB as a chip select signal during configuration read and write transactions. Device Select. When the Device Select signal is actively driven by the 82546EB, it signals notifies the bus master that it has decoded its address as the target of the current access. As an input, DEVSEL# indicates whether any device on the bus has been selected. VIO. The VIO signal is a voltage reference for the PCI interface (3.3 V or 5 V PCI signaling environment). It is used as the clamping voltage. Note: An external resistor is required between the voltage reference and the VIO pin. The target resistor value is 100 K
CBE[7:0]#
TS
PAR
TS
PAR64
TS
FRAME#
STS
IRDY#
STS
TRDY#
STS
STOP#
STS
IDSEL#
I
DEVSEL#
STS
VIO
P
Datasheet
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82546EB -- Networking Silicon
3.2.2
Arbitration Signals
Symbol REQ64#
Type TS
Name and Function Request Transfer. The Request Transfer signal is generated by the current initiator indicating its desire to perform a 64-bit transfer. REQ64# has the same timing as the Frame signal. Acknowledge Transfer. The Acknowledge Transfer signal is generated by the currently addressed target in response to the REQ64# assertion by the initiator. ACK64# has the same timing as the Device Select signal. Request Bus. The Request Bus signal is used to request control of the bus from the arbiter. This signal is point-to-point. Grant Bus. The Grant Bus signal notifies the 82546EB that bus access has been granted. This is a point-to-point signal. Lock Bus. The Lock Bus signal is asserted by an initiator to require sole access to a target memory device during two or more separate transfers. The 82546EB device does not implement bus locking.
ACK64#
TS
REQ# GNT#
TS I
LOCK#
I
3.2.3
Interrupt Signals
Symbol INTA# INTB#
Type TS TS
Name and Function Interrupt A. Interrupt A is used to request an interrupt by port 1 of the. It is an active low, level-triggered interrupt signal. Interrupt B. Interrupt B is used to request an interrupt by port 2 of the 82546EB. It is an active low, level-triggered interrupt signal.
3.2.4
System Signals
Symbol
Type PCI Clock. 82546EB
Name and Function
CLK
I
M66EN
I
66 MHz Enable.
RST#
I
PCI Reset. When the PCI Reset signal is asserted, all PCI output signals, except the Power Management Event signal (PME#), are floated and all input signals are ignored. The PME# context is preserved, depending on power management settings. Most of the internal state of the 82546EB is reset on the de-assertion (rising edge) of RST#.
LAN_ PWR_ GOOD
I
Power Good (Power-on Reset). The Power Good signal is used to indicate that stable power is available for the 82546EB. When the signal is low, the 82546EB holds itself in reset state and floats all PCI signals.
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Datasheet
Networking Silicon -- 82546EB
3.2.5
Error Reporting Signals
Symbol SERR#
Type OD
Name and Function System Error. The System Error signal is used by the 82546EB controller to report address parity errors. SERR# is open drain and is actively driven for a single PCI clock when reporting the error. Parity Error. The Parity Error signal is used by the 82546EB controller to report data parity errors during all PCI transactions except by a Special Cycle. PERR# is sustained tri-state and must be driven active by the 82546EB controller two data clocks after a data parity error is detected. The minimum duration of PERR# is one clock for each data phase a data parity error is present.
PERR#
STS
3.2.6
Power Management Signals
Symbol
Type
Name and Function Power Management Event. The 82546EB device drives this signal low when it receives a wake-up event and either the PME Enable bit in the Power Management Control/Status Register or the Advanced Power Management Enable (APME) bit of the Wake-up Control Register (WUC) is 1b. Auxiliary Power. If the Auxiliary Power signal is high, then auxiliary power is available and the 82546EB device should support the D3cold power state.
PME#
OD
AUX_PWR
I
3.2.7
Impedance Compensation Signals
Symbol
Type
Name and Function N Device Impedance Compensation. This signal should be connected to an external precision resistor (to VDD) that is indicative of the PCI/PCI-X trace load. This cell is used to dynamically determine the drive strength required on the N-channel transistors in the PCI/PCI-X I/O cells. The internal pull-up impedance is nominally 20 K with a minimum of 15 K. P Device Impedance Compensation. This signal should be connected to an external precision resistor (to VSS) that is indicative of the PCI/PCI-X trace load. This cell is used to dynamically determine the drive strength required on the P-channel transistors in the PCI/PCI-X I/O cells. The internal pull-up impedance is nominally 20 K with a minimum of 15 K.
ZN_COMP
I/O
ZP_COMP
I/O
3.2.8
SMB Signals
Symbol SMBCLK SMBDATA SMBALRT#
Type I/O I/O O
Name and Function SMB Clock. The SMB Clock signal is an open drain signal for serial SMB interface. SMB Data. The SMB Data signal is an open drain signal for serial SMB interface. SMB Alert. The SMB Alert signal is open drain for serial SMB interface.
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82546EB -- Networking Silicon
3.3
EEPROM Interface Signals
Symbol EE_DI EE_DO EE_CS EE_SK Type O I O O Name and Function EEPROM Data Input. The EEPROM Data Input pin is used for output to the memory device. EEPROM Data Output. The EEPROM Data Output pin is used for input from the memory device. The EE_DO includes an internal pull-up resistor. EEPROM Chip Select. The EEPROM Chip Select signal is used to enable the device. EEPROM Serial Clock. The EEPROM Shift Clock provides the clock rate for the EEPROM interface, which is approximately 1 MHz.
3.4
Flash Interface Signals
Symbol FL_ADDR [18:0] FL_CS# FL_OE# FL_WE# FL_DATA [7:2] Type O O O O TS Name and Function Flash Address Output. The Flash Address Output signals are used for a Flash or Boot ROM device. Flash Chip Select. The Flash Chip Select signal is used to enable the Flash or Boot ROM device. Flash Output Enable. The Flash Output Enable signal is used to enable the Flash buffers. Flash Write Enable Output. The Flash Write ENable Output signals are used for write cycles. Flash Data I/O. The Flash Data I/O signals are bi-directional and used for Flash data. These signals include internal pull-up devices. Flash Data I/O [1:0] / LAN Port Disable. These pins are inputs from the Flash memory. Alternatively, they can be used to disable the LAN A or LAN B port from a system Super I/O General (GP) port. (FL_DATA[1] corresponds to LAN B, and FL_DATA[0], to LAN A.) They have internal pull-up devices. If the 82546EB is not using Flash functionality, these pins should be connected to external pull-up resistors. If the pins are used as LAN_DISABLE#, the device transitions to a low power state, and the corresponding LAN port is disabled when its pin is sampled low on the rising edge of PCI reset.
FL_DATA [1:0]/ LAN_DISA BLE#
TS
3.5
3.5.1
Miscellaneous Signals
LED Signals
Symbol ACT_A# LINK_A# LINKA100#
Type O O O
Name and Function Activity A. The Activity LED signal flashes an LED to indicate receive activity on port 1 (port A) only for packets destined for this node. Link A. The Link LED signal indicates link connectivity on port 1 (port A). Link A 100. The Link 100 signal drives an LED indicating link at 100 Mbps on port 1 (port A).
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Datasheet
Networking Silicon -- 82546EB
Symbol LINKA1000# ACT_B# LINK_B# LINKB100# LINKB1000#
Type O O O O O
Name and Function Link A 1000. The Link 1000 signal drives an LED indicating link at 1000 Mbps on port 1 (port A). Activity B. The Activity LED signal flashes an LED to indicate activity on port 2 (port B) only for packets destined for this node. Link B. The Link LED signal indicates link connectivity on port 2 (port B). Link B 100. The Link 100 signal drives an LED indicating link at 100 Mbps on port 2 (port B). Link B 1000. The Link 1000 signal drives an LED indicating link at 1000 Mbps on port 2 (port B).
3.5.2
Software Definable Signals
Symbol
Type
Name and Function Software Defined Pin. The Software Defined Pins are reserved and programmable with respect to input and output capability. These default to input signals upon power-up but may be configured differently by the EEPROM. The upper four bits may be mapped to the General Purpose Interrupt bits if they are configured as input signals. Note: SDP5 is not included in the group of Software Defined Pins.
SDP[7:6] SDP[1:0]
TS
3.6
3.6.1
PHY Signals
Crystal Signals
Symbol XTAL1
Type I
Name and Function Crystal One. The Crystal One pin is a 25 MHz +/- 50 ppm input signal. It can be connected to either an oscillator or crystal. If a crystal is used, Crystal Two (XTAL2) must also be connected. Crystal Two. Crystal Two is the output of an internal oscillator circuit used to drive a crystal into oscillation. If an external oscillator is used in the design, XTAL2 must be disconnected.
XTAL2
O
Datasheet
13
82546EB -- Networking Silicon
3.6.2
PHY Analog Signals
Symbol REF_A
Type P
Name and Function Reference A. This Reference signal should be connected to VSS through an external 2.49 K resistor. Media Dependent Interface A [0].
1000BASE-T: In MDI configuration, MDIA[0]+/- corresponds to BI_DA+/-, and in MDI-X
configuration, MDIA[0]+/- corresponds to BI_DB+/-. MDIA[0]+/A
100BASE-TX: In MDI configuration, MDIA[0]+/- is used for the transmit pair, and in MDI-
X configuration, MDIA[0]+/- is used for the receive pair. 10BASE-T: In MDI configuration, MDIA[0]+/- is used for the transmit pair, and in MDI-X configuration, MDIA[0]+/- is used for the receive pair. Media Dependent Interface A [1].
1000BASE-T: In MDI configuration, MDIA[1]+/- corresponds to BI_DB+/-, and in MDI-X
configuration, MDIA[1]+/- corresponds to BI_DA+/-. MDIA[1]+/A
100BASE-TX: In MDI configuration, MDIA[1]+/- is used for the receive pair, and in MDI-X
configuration, MDIA[1]+/- is used for the transit pair. 10BASE-T: In MDI configuration, MDIA[1]+/- is used for the receive pair, and in MDI-X configuration, MDIA[1]+/- is used for the transit pair. Media Dependent Interface A [2].
1000BASE-T: In MDI configuration, MDIA[2]+/- corresponds to BI_DC+/-, and in MDI-X
MDIA[2]+/-
A
configuration, MDIA[2]+/- corresponds to BI_DD+/-.
100BASE-TX: Unused.
10BASE-T: Unused. Media Dependent Interface A [3].
1000BASE-T: In MDI configuration, MDIA[3]+/- corresponds to BI_DD+/-, and in MDI-X
MDIA[3]+/-
A
configuration, MDIA[3]+/- corresponds to BI_DC+/-.
100BASE-TX: Unused.
10BASE-T: Unused. REF_B P Reference B. This Reference signal should be connected to VSS through an external 2.49 K resistor. Media Dependent Interface B [0].
1000BASE-T: In MDI configuration, MDIB[0]+/- corresponds to BI_DA+/-, and in MDI-X
configuration, MDIB[0]+/- corresponds to BI_DB+/-. MDIB[0]+/A
100BASE-TX: In MDI configuration, MDIB[0]+/- is used for the transmit pair, and in MDI-
X configuration, MDIB[0]+/- is used for the receive pair. 10BASE-T: In MDI configuration, MDIB[0]+/- is used for the transmit pair, and in MDI-X configuration, MDIB[0]+/- is used for the receive pair.
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Datasheet
Networking Silicon -- 82546EB
Symbol
Type
Name and Function Media Dependent Interface B [1].
1000BASE-T: In MDI configuration, MDIB[1]+/- corresponds to BI_DB+/-, and in MDI-X
configuration, MDIB[1]+/- corresponds to BI_DA+/-. MDIB[1]+/A
100BASE-TX: In MDI configuration, MDIB[1]+/- is used for the receive pair, and in MDI-X
configuration, MDIB[1]+/- is used for the transit pair. 10BASE-T: In MDI configuration, MDIB[1]+/- is used for the receive pair, and in MDI-X configuration, MDIB[1]+/- is used for the transit pair. Media Dependent Interface B [2].
1000BASE-T: In MDI configuration, MDIB[2]+/- corresponds to BI_DC+/-, and in MDI-X
MDIB[2]+/-
A
configuration, MDIB[2]+/- corresponds to BI_DD+/-.
100BASE-TX: Unused.
10BASE-T: Unused. Media Dependent Interface B [3].
1000BASE-T: In MDI configuration, MDIB[3]+/- corresponds to BI_DD+/-, and in MDI-X
MDIB[3]+/-
A
configuration, MDIB[3]+/- corresponds to BI_DC+/-.
100BASE-TX: Unused.
10BASE-T: Unused.
3.7
Serializer / Deserializer Signals
Symbol RXA+/RXB +/TXA+/TXB +/SIG_ DETECT (A and B) Type I Name and Function SERDES Receive Pairs A and B. These signals make the differential receive pair for the 1.25 GHz serial interface. If the SERDES interface is not used, these pins should not be connected. SERDES Transmit Pairs A and B. These signals make the differential transmit pair for the 1.25 GHz serial interface. If the SERDES interface is not used, these pins should not be connected. Signal Detects A and B. These pins indicate whether the SERDES signals (connected to the 1.25 GHz serial interface) have been detected by the optical transceivers. If the SERDES interface is not used, the SIG_DETECT inputs should be connected to ground using pull-down resistors.
O
I
3.8
JTAG Test Interface Signals
Symbol JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS Type I I O I JTAG Clock. JTAG TDI. JTAG TDO. JTAG TMS. Name and Function
Datasheet
15
82546EB -- Networking Silicon
Symbol JTAG_ TRST# CLK_VIEW TEST*
Type I O I
Name and Function JTAG Reset. This is an active low reset signal for JTAG. This signal should be terminated using a pull-down resistor to ground. It must not be left unconnected. Clock View. The Clock View signal is an output of clock signals required for IEEE testing. Factory Test Pin.
3.9
3.9.1
Power Supply Connections
Power Support Signals
Symbol CTRL_15 CTRL_25A CTRL_25B
Type O O O
Name and Function 1.5 V Control. The 1.5 V Control signal is an output to an external power transistor. If regulators are used, it should be left unconnected. 2.5 V Control. The 2.5 V Control signal is an output to an external power transistor. If regulators are used, it should be left unconnected. 2.5 V Control. The 2.5 V Control signal is an output to an external power transistor. If regulators are used, it should be left unconnected.
3.9.2
Digital Supplies
Symbol VDDO DVDD
Type P P 3.3 V I/O Power Supply.
Name and Function
1.5 V Digital Core Power Supply.
3.9.3
Analog Supplies
Symbol AVDDH AVDDLA AVDDLB
Type P P P 3.3 V Analog Power Supply.
Name and Function
2.5 V Analog Power Supply to Port A. 2.5 V Analog Power Supply to Port B.
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Datasheet
Networking Silicon -- 82546EB
3.9.4
Ground and No Connects
Symbol GND NC Reserved
Type P P R Ground.
Name and Function
No Connect. Do not connect any circuitry to these pins. Pull-up or pull-down resistors should not be connected to these pins. Reserved. These pins are reserved for factory purposes and should be pulled down to ground through a pull-down resistor.
Datasheet
17
82546EB -- Networking Silicon
4.0
Note:
Voltage, Temperature, and Timing Specifications
The specification values listed in this section are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design.
4.1
Table 1.
Targeted Absolute Maximum Ratings
Absolute Maximum Ratingsa
Symbol VDD (3.3) VDD (2.5) VDD (1.5) VDD VI / VO VI / VO Parameter DC supply voltage on VDDD or AVDDH with respect to VSS DC supply voltage on AVDDL with respect to VSS DC supply voltage on DVDD with respect to VSS DC supply voltage LVTTL input voltage 5 V compatible input voltage DC output current (by cell type): IO IOL = 3 mA IOL = 6 mA IOL - 12 mA TSTG Storage temperature range ESD per MIL_STD-883 Test Method 3015, Specification 2001V Latchup Over/Undershoot: 150 mA, 125 C -40 10 20 40 125 VDD overstress: VDD(3.3)(7.2 V) C mA Min VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 VSS - 0.5 Max 4.6 4.6 or VDD (2.5) + 0.5b 4.6 or VDD (2.5) + 0.5c 4.6 4.6 6.6 Unit V V V V V V
V
a. Maximum ratings are referenced to ground (VSS). Permanent device damage is likely to occur if the ratings in this table are exceeded. These values should not be used as the limits for normal device operations. b. The maximum value is the lesser value of 4.6 V or VDD(2.5) + 0.5 V. This specification applies to biasing the device to a steady state for an indefinite duration. During normal device power-up, explicit power sequencing is not required. c. The maximum value is the lesser value of 4.6 V or VDD(2.5) + 0.5 V.
4.2
Table 2.
Recommended Operating Conditions
Recommended Operating Conditionsa
Symbol VDD (3.3) VDD (2.5) VDD (1.5) VIO Parameter DC supply voltage on VDDD or AVDDH b DC supply voltage on AVDDLc DC supply voltage on DVDD PCI bus voltage reference Min 3.0 2.38 1.43 3.0 Max 3.6 2.62 1.57 5.25 Unit V V V V
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Datasheet
Networking Silicon -- 82546EB
Table 2.
Recommended Operating Conditionsa
Symbol tR / tF tr/tf TA TJ Parameter Input rise/fall time (normal input) input rise/fall time (Schmitt input) Operating temperature range (ambient) Junction temperature Min 0 0 0 Max 200 10 55 125 Unit ns ms C C
a. Sustained operation of the device at conditions exceeding these values, even if they are within the absolute maximum rating limits, might result in permanent damage. b. It is recommended for VDDO to equal AVDDH (VDDO = AVDDH) during power-up and normal operation. c. It is recommended for both VDDO and AVDDH to be of a value greater than AVDDL, with a value greater than DVDD, during power-up (VDDO or AVDDH > AVDDL > DVDD). However, voltage sequencing is not a strict requirement if the power supply ramp must be faster than approximately 200 ms.
4.3
Table 3.
DC Specifications
DC Characteristics
Symbol VDD (3.3) VDD (2.5) VDD (1.5) Parameter DC supply voltage on VDDO or AVDDH DC supply voltage on AVDDL DC supply voltage on DVDD Min 3.00 2.38 1.43 Typ 3.3 2.5 1.5 Max 3.60 2.62 1.57 Units V V V
Table 4.
Power Supply Characteristics
D0a (both ports) Unplugged/No Link Typa Icc (mA) 3.3 V 2.5 V 1.5 V Total Device Power 65 40 180 600 mW Maxb Icc (mA) 80 45 190 10 Mbps Operation Typ Icc (mA) 100 95 160 800 mW Max Icc (mA) 110 100 170 100 Mbps Operation Typ Icc (mA) 115 100 200 950 mW Max Icc (mA) 120 105 220 1000 Mbps Operation Typ Icc (mA) 240 280 740 1.6 W Max Icc (mA) 265 290 840 3.1 W
a. Typical conditions: operating temperature (TA) = 25 C, nominal voltages, moderate network traffic at full duplex, and PCI 66 MHz system interface. b. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network traffic at full duplex, and PCI-X 100 to 133 MHZ system interface.
Datasheet
19
82546EB -- Networking Silicon
D3cold - Wake Up Enabled (both ports) Unplugged/No Link Typa Icc (mA) 3.3 V 2.5 V 1.5 V Total Device Power 65 40 50 400 mW Maxb Icc (mA) 75 45 50 10 Mbps Operation Typ Icc (mA) 100 40 60 525 mW Max Icc (mA) 110 45 65 100 Mbps Operation Typ Icc (mA) 95 100 105 725 mW Max Icc (mA) 120 125 130
D3cold - Wake Up Disabled (both ports) Typ Icc (mA) 65 40 20 350 mW Max Icc (mA) 75 45 40
a. Typical conditions: operating temperature (TA) = 25 C, nominal voltages, moderate network traffic at full duplex, and PCI 66 MHz system interface. b. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network traffic at full duplex, and PCI-X 100 to 133 MHZ system interface.
Uninitialized/Disabled D(n) Uninitialized (LAN PWR GOOD = 0) Typa Icc (mA) 3.3 V 2.5 V 1.5 V Total Device Power 75 75 360 1.0 W Maxb Icc (mA) 80 80 385 Disabled (via Flash Address) Typ Icc (mA) 25 35 160 400 mW Max Icc (mA) 25 35 175
a. Typical conditions: operating temperature (TA) = 25 C, nominal voltages, moderate network traffic at full duplex, and PCI 66 MHz system interface. b. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network traffic at full duplex, and PCI-X 100 to 133 MHZ system interface.
Complete Subsystem (including magnetics, LED, and regulator circuits) D3cold / Wake disabled Typa Icc (mA) 3.3 V 2.5 V 1.5 V Subsystem 3.3 V Current 65 40 20 75 45 40 160 mA Maxb Icc (mA) D3cold / Wake enabled at 10 Mbps Typ Icc (mA) 110 60 60 Max Icc (mA) 120 65 65 250 mA D3cold / Wake enabled at 100 Mbps Typ Icc (mA) 115 150 105 Max Icc (mA) 140 175 130 445 mA D0 at 1000 Mbps Typ Icc (mA) 245 470 740 Max Icc (mA) 270 480 840 1.6 A
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Datasheet
Networking Silicon -- 82546EB
a. Typical conditions: operating temperature (TA) = 25 C, nominal voltages, moderate network traffic at full duplex, and PCI 66 MHz system interface. b. Maximum conditions: minimum operating temperature (TA) values, maximum voltage values, continuous network traffic at full duplex, and PCI-X 100 to 133 MHZ system interface.
4.4
Table 5.
AC Characteristics
AC Characteristics: 3.3 V Interfacing
Symbol fPCICLK fPCICLK Parameter Clock frequency in PCI mode Clock frequency in PCI-X mode 66 Min Typ Max 66 133 Unit MHz MHz
Table 6.
25 MHz Clock Input Requirements
Symbol fi_TX_CLK Parametera TX_CLK_IN frequency Min 25 - 50 ppm Typ 25 Max 25 + 50 ppm Unit MHz
a. This parameter applies to an oscillator connected to the Crystal One (XTAL1) input. Alternatively, a crystal may be connected to XTAL1 and XTAL2 as the frequency source for the internal oscillator.
Table 7.
Link Interface Clock Requirements
Symbol fGTXa Parameter GTX_CLK frequency Min Typ 125 Max Unit MHz
a. GTX_CLK is used externally for test purposes only.
Table 8.
EEPROM Interface Clock Requirements
Symbol fSK Parameter Min Typ Max 1 Unit MHz
Table 9.
AC Test Loads for General Output Pins
Symbol CL CL CL CL TDO APM_WAKEUP, PME#, SDP[7:0] EE_DI, EE_SK, FL_ADDR[18:0], FL_CS#, FL_OE#, FL_WE#, FL_DATA[7:0] RX_ACTIVITY, TX_ACTIVITY, LINK_UP Signal Name Value 10 16 18 20 Units pF pF pF pF
Datasheet
21
82546EB -- Networking Silicon
Figure 2. AC Test Loads for General Output Pins
CL
4.5
Serial Interface Specifications
Table 10. Driver Characteristics
Symbol VOD VOS Delta VOD RO ISA, ISB ISAB Parameter Differential Output Voltage Swinga Output Offset Voltage Change in VOD between 0 and 1b Differential Output Impedance Output Current on Short to VSS Output Current when A and B are Shorted 80 Min 315 1075 Typ Max 750 1325 25 120 40 12 Units mV peakpeak mV mV mA mA
a. This is the maximum inside dimension of the eye pattern, measured on high and low data patterns with pre-emphasis present. Load = 100 . b. This is defined as an absolute value of amplitude jitter.
Table 11. Receiver Characteristics
Symbol V ID R IN Parameter Differential Input Voltage Swing Differential Input Impedance Min 100 Typ Max 2000 Units mV peakpeak
80
120
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Datasheet
Networking Silicon -- 82546EB
4.6 4.6.1
4.6.1.1
Timing Specifications PCI/PCI-X Bus Interface
PCI/PCI-X Bus Interface Clock
Table 12. PCI/PCI-X Bus Interface Clock Parameters
a
Symbol
Parameter
PCI-X 133 MHz Min Max 20
PCI-X 66 MHz Min 15 6 6 Max 20
PCI 66MHz Min 15 6 6 Max 30
PCI 33 MHz Units Min 30 11 11 Max ns ns ns 4 V/ns mV/ns
TCYC TH TL
CLK cycle time CLK high time CLK low time CLK slew rate RST# slew rateb
7.5 3 3 1.5 50
4
1.5 50
4
1.5 50
4
1 50
a. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown. b. The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system noise cannot render a monotonic signal to appear bouncing in the switching range.
Figure 3. PCI/PCI-X Clock Timing
Tcyc
3.3 V Clock
Th 0.6 Vcc
0.4 Vcc p-to-p (minimum)
0.5 Vcc 0.4 Vcc 0.3 Vcc
0.2 Vcc Tl
4.6.1.2
PCI/PCI-X Bus Interface Timing
Table 13. PCI/PCI-X Bus Interface Timing Parameters
PCI-X 133 MHz Min TVAL TVAL (ptp) TON TOFF CLK to signal valid delay: bussed signals CLK to signal valid delay: point-to-point signals Float to active delay Active to float delay 0.7 0.7 0 7 Max 3.8 3.8 PCI-X 66 MHz Min 0.7 0.7 0 7 Max 3.8 3.8 PCI 66MHz Min 2 2 2 14 Max 6 6 PCI 33 MHz Units Min 2 2 2 28 Max 11 12 ns ns ns ns
Symbol
Parameter
Datasheet
23
82546EB -- Networking Silicon
Table 13. PCI/PCI-X Bus Interface Timing Parameters
PCI-X 133 MHz Min TSU TSU (ptp) TH TRRSU TRRH Input setup time to CLK: bussed signals Input setup time to CLK: point-to-point signals Input hold time from CLK REQ64# to RST# setup time RST# to REQ64# hold time 1.2 1.2 0.5 10*
TCYC
PCI-X 66 MHz Min 1.7 1.7 0.5 10*
TCYC
PCI 66MHz Min 3 5 0 10*
TCYC
PCI 33 MHz Units Min 7 10, 12 0 10*
TCYC
Symbol
Parameter
Max
Max
Max
Max ns ns ns ns ns
0
0
0
0
NOTES: 1. Output timing measurements are as shown. 2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed. 3. Input timing measurements are as shown.
Table 13. PCI Bus Interface Timing Measurement Conditions
Symbol VTH VTL VTEST Parameter Input measurement test voltage (high) Input measurement test voltage (low) Output measurement test voltage Input signal slew rate PCI-X 0.6*VCC 0.25*VCC 0.4*VCC 1.5 PCI 66 MHz 3.3 v 0.6*VCC 0.2*VCC 0.4*VCC 1.5 Unit V V V V/ns
Figure 4. PCI Bus Interface Output Timing Measurement
VTH PCI_CLK VTEST VTL
Output Delay
output current leakage current
VTEST VSTEP (3.3V Signalling)
Tri-State Output TON TOFF
24
Datasheet
Networking Silicon -- 82546EB
Figure 5. PCI Bus Interface Input Timing Measurement Conditions
VTH PCI_CLK VTEST VTL TSU VTH Input VTL VTEST Input Valid VTEST VMAX TH
Figure 6. TVAL (max) Rising Edge Test Load
Pin 1/2 inch max. Test Point
25 10 pF
Datasheet
25
82546EB -- Networking Silicon
Figure 7. TVAL (max) Falling Edge Test Load
Pin 1/2 inch max. Test Point
25 10 pF
VCC
4.6.2
4.6.2.1
Link Interface Timing
Link Interface Rise and Fall Time
Table 14. Rise and Fall Times
Symbol TR TF TR TF Parameter Clock rise time Clock fall time Data rise time Data fall time Condition 0.8 V to 2.0 V 2.0 V to 0.8 V 0.8 to 2.0 V 2.0 V to 0.8 V Min 0.7 0.7 0.7 0.7 Max Unit ns ns ns ns
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Networking Silicon -- 82546EB
Figure 8. Link Interface Rise/Fall Timing
2.0 V
0.8 V
TR
TF
4.6.2.2
Link Interface Transmit Timing
Figure 9. Transmit Interface Timing
TX_CLOCK
1.4V
TSU
TH
TX_DATA[9:0]
Valid Data
TPERIOD
Table 15. Transmit Interface Timing
Symbol TPERIOD TSETUP THOLD TDUTY Parameter GTX_CLK perioda TBI mode (1000 Mbps) Data setup to rising GTX_CLK Data hold from rising GRX_CLK GTX_CLK duty cycle 40 Min Typ 8 2.5 1.0 60 Max Unit ns ns ns %
a. GTX_CLK should have a 100 ppm tolerance.
Datasheet
27
82546EB -- Networking Silicon
4.6.2.3
Link Interface Receive Timing
Figure 10. Receive Interface Timing
RBC1
1.4V
TSU 2.0V RX_DATA[9:0] 0.8V 2.0V COM_DET 0.8V TA-B COMMA Code_Group
TH Valid Data
TSU
TH 1.4V
RBC0
Table 16. Receive Interface Timing
Symbol TREQ TSETUP THOLD TDUTY TA-B Parameter RBC0/RBC1 frequency TBI mode (1000 Mbps) Data setup before rising RBC0/RBC1 Data hold after rising RBC0/RBC1 RBC0/RBC1 duty cycle RBC0/RBC1 skew 40 7.5 Min Typ 62.5 2.5 1 60 8.5 Max Unit MHz ns ns % ns
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Datasheet
Networking Silicon -- 82546EB
4.6.3
Flash Interface
Figure 11. Flash Read Timing
0ns
250ns
Flash CE# Flash OE# Flash WE# Flash Address [18:0] Flash Data
Table 17. Flash Read Operation Timing
Symbol TCE TACC THOLD Parameter Flash CE# or OE# to read data delay Flash address setup time Data hold time 0 Min Typ Max 160 160 Unit ns ns ns
Figure 12. Flash Write Timing
0ns
250ns
500ns
Flash CE# Flash OE# Flash WE# Flash Address [18:0] Flash Data
Datasheet
29
82546EB -- Networking Silicon
Table 18. Flash Write Operation Timing
Symbol TWE TAH TDS Parameter Flash write pulse width (WE#) Flash address hold time Flash data setup time 0 160 Min Typ 160 Max Unit ns ns ns
4.6.4
EEPROM Interface
Table 19. Link Interface Clock Requirements
Symbol TPW Parameter EE_SK pulse width Min Typ
TPERIOD*128
Max
Unit ns
Table 20. Link Interface Clock Requirements
Symbol TDOS TDOH Parametera EE_DO setup time EE_DO hold time Min TCYC*2 0 Typ Max Unit ns ns
30
.KS_EE_O ot decnerefer si tub emit elcyc KLC eht fo noitcnuf a si emit dloh dna putes OD_EE ehT .a
Datasheet
Networking Silicon -- 82546EB
5.0
5.1
Package and Pinout Information
Device Identification
Figure 13. 82546EB Device Identification Markings
FW82546EB Intel (C) '02 YYWW Country A1 Tnnnnnnnn
82546EB YYWW Tnnnnnnnn (c)'02 Country
Product Name Date Code Lot Trace Code Copyright Information Country of Origin Assembly
NOTE: The black mark in the lower left corner indicates the location of pin 1.
Datasheet
31
82546EB -- Networking Silicon
5.2
Package Information
The 82546EB device is a 364-lead ball grid array (BGA) measuring 21 mm2. The package dimensions are detailed in Figure 14. The nominal ball pitch is 1 mm.
Figure 14. 82546EB Mechanical Specifications
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Datasheet
Networking Silicon -- 82546EB
5.3
Thermal Specifications
The 82546EB device is specified for operation when the ambient temperature (TA) is within the range of 0 C to 55 C. The maximum permitted junction temperature is 120 C. TC (case temperature) is calculated using the equation: TC = TA + P (qJA - q JC) TJ (junction temperature) is calculated using the equation: TJ = TA + P qJA The power consumption (P) is calculated by using the typical ICC and nominal VCC. The thermal resistances are shown in Table 21.
Table 21. Thermal Characteristics
Value at specified airflow (m/s) Symbol Parameter 0 qJA qJC Thermal resistance, junction-toambient Thermal resistance, junction-tocase 17.7 6.8 1 15.6 6.8 2 14.8 6.8 3 14.0 6.8 C/Watt C/Watt Units
Thermal resistances are determined empirically with test devices mounted on standard thermal test boards. Real system designs may have different characteristics due to board thickness, arrangement of ground planes, and proximity of other components. The case temperature measurements should be used to assure that the 82546EB device is operating under recommended conditions.
Datasheet
33
82546EB -- Networking Silicon
5.4
Note:
Ball Mapping Diagram
The 82546EB device uses five categories of VDD connections: VDDO (3.3 V), AVDDH (Analog 3.3 V), AVDDL (Analog 2.5 V), and DVDD (1.5 V).
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
A B C D E F G H J K L M N P R T U V W Y
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Datasheet
Networking Silicon -- 82546EB
5.5
Pinout Information
Table 22. PCI Address, Data, and Control Signals
Signal PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] PCI_AD[16] PCI_AD[17] PCI_AD[18] PCI_AD[19] PCI_AD[20] PCI_AD[21] PCI_AD[22] PCI_AD[23] PCI_AD[24] PCI_AD[25] PCI_AD[26] PCI_AD[27] Pin T14 V14 Y15 W14 T13 V13 Y14 U12 V12 T12 W12 Y12 V11 T11 Y11 W10 U8 Y7 Y6 V7 T7 W6 Y5 V6 U6 V5 W4 V4 Signal PCI_AD[28] PCI_AD[29] PCI_AD[30] PCI_AD[31] PCI_AD[32] PCI_AD[33] PCI_AD[34] PCI_AD[35] PCI_AD[36] PCI_AD[37] PCI_AD[38] PCI_AD[39] PCI_AD[40] PCI_AD[41] PCI_AD[42] PCI_AD[43] PCI_AD[44] PCI_AD[45] PCI_AD[46] PCI_AD[47] PCI_AD[48] PCI_AD[49] PCI_AD[50] PCI_AD[51] PCI_AD[52] PCI_AD[53] PCI_AD[54] PCI_AD[55] Pin Y3 U4 V3 V1 L16 M20 M19 M16 M18 M17 N20 N16 P20 N18 P19 P16 R20 P18 P17 T20 R16 U20 R18 T19 V20 T18 W20 V19 Signal PCI_AD[56] PCI_AD[57] PCI_AD[58] PCI_AD[59] PCI_AD[60] PCI_AD[61] PCI_AD[62] PCI_AD[63] CBE[0]# CBE[1]# CBE[2]# CBE[3]# CBE[4]# CBE[5]# CBE[6]# CBE[7]# PAR PAR64 FRAME# IRDY# TRDY# STOP# IDSEL DEVSEL# VIO VIO Pin T17 U18 V18 U16 V17 W18 Y19 T16 Y13 V10 T8 Y4 V16 Y18 Y17 T15 U10 V15 V8 W8 Y8 V9 T6 T9 Y1 Y20
Table 23. PCI Arbitration Signals
Signal REQ64# ACK64# Pin U14 W16 REQ# GNT# Signal Pin W2 T3 LOCK# Signal Pin Y9
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35
82546EB -- Networking Silicon
Table 24. Interrupt Signals
Signal INTA# Pin Y2 Signal INTB# Pin T1
Table 25. System Signals
Signal PCICLK M66EN Pin U2 Y16 PCIRST# LAN_PWR_GOOD Signal Pin T5 A17
Table 26. Error Reporting Signals
Signal SERR# Pin T10 PERR# Signal Pin Y10
Table 27. Power Management Signals
Signal PME# Pin T4 Signal AUX_PWR Pin R3
Table 28. Impedance Compensation Signals
Signal ZN_COMP Pin T2 Signal ZP_COMP Pin R5
Table 29. SMB Signals
Signal SMBCLK Pin A14 Signal SMBDATA Pin A15 Signal SMBALRT# Pin A16
Table 30. EEPROM Interface Signals
Signal EE_DI EE_DO Pin C19 B20 EE_CS EE_SK Signal Pin C20 D20
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Networking Silicon -- 82546EB
Table 31. Flash Interface Signals
Signal FL_ADDR[0] FL_ADDR[1] FL_ADDR[2] FL_ADDR[3] FL_ADDR[4] FL_ADDR[5] FL_ADDR[6] FL_ADDR[7] FL_ADDR[8] FL_ADDR[9] Pin F16 E18 E16 E15 E14 E13 D15 B16 F17 F18 Signal FL_ADDR[10] FL_ADDR[11] FL_ADDR[12] FL_ADDR[13] FL_ADDR[14] FL_ADDR[15] FL_ADDR[16] FL_ADDR[17] FL_ADDR[18] FL_CS# Pin G17 G16 B15 D19 D18 C15 D16 C18 D17 H20 FL_OE# FL_WE# FL_DATA[0] / LAN_A_DISABLE FL_DATA[1] / LAN_B_DISABLE FL_DATA[2] FL_DATA[3] FL_DATA[4] FL_DATA[5] FL_DATA[6] FL_DATA[7] Signal Pin K18 C17 H16 G18 J16 H18 J17 J18 K17 K16
Table 32. LED Signals
Signal ACT_A# LINK_A# LINKA100# Pin N1 M1 N4 Signal LINKA1000# ACT_B# LINK_B# Pin N3 B13 A13 Signal LINKB100# LINKB1000# Pin C14 C13
Table 33. Software Definable Signals
Signal SDPA[0] SDPA[1] SDPA[6] SDPA[7] Pin G4 G5 E12 E11 SDPB[0] SDPB[1] SDPB[6] SDPB[7] Signal Pin D13 B12 C12 D12
Table 34. Crystal Signals
Signal XTAL1 Pin A3 XTAL2 Signal Pin A4
Table 35. PHY Signals
Signal REF_A REF_B MDIA0Pin E3 L4 B1 MDIA2MDIA2+ MDIA3Signal Pin D1 D2 E1 MDIB1MDIB1+ MDIB2Signal Pin L1 K1 J2
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82546EB -- Networking Silicon
Table 35. PHY Signals
Signal MDIA0+ MDIA1MDIA1+ Pin B2 C1 C2 MDIA3+ MDIB0MDIB0+ Signal Pin E2 L3 K3 MDIB2+ MDIB3MDIB3+ Signal Pin J1 H3 J3
Table 36. Serializer / Deserializer Signals
Signal RXA+ RXARXB+ RXBPin G19 G20 J19 J20 TXA+ TXATXB+ TXBSignal Pin F19 F20 K19 K20 Signal SIG_DETECT_A SIG_DETECT_B Pin E20 L20
Table 37. JTAG Test Interface Signals
Signal JTAG_TCK JTAG_TDI JTAG_TDO Pin P1 P4 P2 Signal JTAG_TMS JTAG_RST# Pin P5 N5 Signal CLK_VIEW TEST# Pin P3 A8
Table 38. Power Support Signals
Signal CTRL_15 Pin A18 Signal CTRL_25A Pin F2 CTRL_B Signal Pin H5
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Table 39. Digital Power Signals
Signal VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) - PHY B VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) Pin B8 B14 B19 C10 C16 D6 D11 E17 H4 H19 L17 M2 N19 R4 R17 U1 U3 Signal VDDO (3.3V) VDDO (3.3V) - PLL VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) VDDO (3.3V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) Pin U7 U11 U15 U19 W1 W5 W9 W13 W17 G7 G8 G9 G12 G13 G14 H7 H8 Signal DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) Pin H13 H14 J7 J14 M7 M14 N7 N8 N13 N14 P7 P8 P9 P12 P13 P14
Table 40. Analog Power Signals
Signal AVDDH (3.3 V) AVDDH (3.3 V) - PHY A AVDDLA (2.5 V) Pin B4 F1 A19 Signal AVDDLA (2.5 V) AVDDLA (2.5 V) AVDDLA (2.5 V) Pin G1 G2 G3 Signal AVDDLB (2.5 V) AVDDLB (2.5 V) AVDDLB (2.5 V) Pin L2 L5 L18
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82546EB -- Networking Silicon
Table 41. Grounds and No Connect Signals
Signal GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin A1 A2 A5 A10 B3 B6 B11 B17 C3 D3 D8 D14 E19 F3 G10 G11 H2 H9 H10 H11 H12 H17 J8 J9 J10 J11 J12 J13 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Signal Pin K2 K4 K5 K7 K8 K9 K10 K11 K12 K13 K14 L7 L8 L9 L10 L11 L12 L13 L14 L19 M4 M8 M9 M10 M11 M12 M13 N9 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC Signal Pin N10 N11 N12 N17 P10 P11 R2 R19 U5 U9 U13 U17 V2 W3 W7 W11 W15 W19 A11 A12 F4 F5 H1 J4 J5 M3 N2
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Table 42. Reserved Signals
Signal Reserved[0] Reserved[1] Reserved[2] Reserved[3] Reserved[4] Reserved[5] Reserved[6] Reserved[7] Reserved[8] Reserved[9] Pin D4 D5 C4 E4 C5 E5 B5 E6 D7 C7 Signal Reserved[10] Reserved[11] Reserved[12] Reserved[13] Reserved[14] Reserved[15] Reserved[16] Reserved[17] Reserved[18] Reserved[19] Pin E10 B7 A7 C8 E8 E9 D9 C9 B9 D10 Signal Reserved[20] Reserved[21] Reserved[22] Reserved[23] Reserved[24] Reserved[25] Reserved[26] Reserved[27] Reserved[28] Reserved[29] Pin A9 C11 B10 C6 A20 B18 M5 E7 A6 R1
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